View ICS85401_286351.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Integrated Circuit Systems, Inc.
ICS85401
2:1 DIFFERENTIAL-TO-LVDS MULTIPLEXER
FEATURES
* 2:1 LVDS MUX * 1 LVDS output * 2 differential clock inputs can accept: LVPECL, LVDS, CML * Maximum input/output frequency: >2.5GHz * Translates LVCMOS/LVTTL input signals to LVDS levels by using a resistor bias network on nCLK0, nCLK1 * Propagation delay: 460ps (maximum) * Part-to-part skew: 100ps (maximum) * 3.3V operating supply * -40C to 85C ambient operating temperature
GENERAL DESCRIPTION
The ICS85401 is a high performance 2:1 Differential-to-LVDS Multiplexer and a member of the HiPerClockSTM HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS85401 can also perform differential translation because the differential inputs accept LVPECL, CML as well as LVDS levels. The ICS85401 is packaged in a small 3mm x 3mm 16 VFQFN package, making it ideal for use on space constrained boards.
ICS
BLOCK DIAGRAM
CLK0 nCLK0 CLK1 nCLK1 0 Q nQ 1
PIN ASSIGNMENT
GND GND
CLK0 1 nCLK0 2 CLK1 3 nCLK1 4
16 15 14 13 12 11 10 9 5
nc
VDD
nc
GND Q nQ GND
6
CLK_SEL
7
nc
8
VDD
REV. A FEBRUARY 22, 2005
CLK_SEL
ICS85401
16-Lead VFQFN 3mm x 3mm x 0.95 package body K Package Top View
85401AK
www.icst.com/products/hiperclocks.html
1
Integrated Circuit Systems, Inc.
ICS85401
2:1 DIFFERENTIAL-TO-LVDS MULTIPLEXER
Type Input Input Input Input Pulldown Pullup/ Pulldown Pulldown Pullup/ Pulldown Description Non-inver ting differential clock input. Inver ting differential clock input. VDD/2 default when left floating. Non-inver ting differential clock input. Inver ting differential clock input. VDD/2 default when left floating. Unused pins. Clock select input. When HIGH, selects CLK1, nCLK1 inputs. When LOW, selects CLK0, nCLK0 inputs. LVCMOS / LVTTL interface levels. Positive supply pins. Power supply ground. Differential output pair. LVDS interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3 4 5, 7, 16 6 8, 13 9, 12, 14, 15 1 0, 11 Name CLK0 nCLK0 CLK1 nCLK1 nc CLK_SEL VDD GND nQ, Q
Unused Input Power Power Output Pulldown
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 1 37 37 Maximum Units pF k k
TABLE 3. CONTROL INPUT FUNCTION TABLE
Input CLK_SEL 0 1 Clock Out CLK CLK0, nCLK0 CLK1, nCLK1
85401AK
www.icst.com/products/hiperclocks.html
2
REV. A FEBRUARY 22, 2005
Integrated Circuit Systems, Inc.
ICS85401
2:1 DIFFERENTIAL-TO-LVDS MULTIPLEXER
4.6V -0.5V to VDD + 0.5 V 10mA 15mA 51.5C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V 5%, TA = -40C TO 85C
Symbol VDD IDD Parameter Positive Supply Voltage Power Supply Current Test Conditions Minimum 3.135 Typical 3.3 Maximum 3.465 40 Units V mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V 5%, TA = -40C TO 85C
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current CLK_SEL CLK_SEL CLK_SEL CLK_SEL VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V -150 Test Conditions Minimum 2 -0.3 Typical Maximum VDD + 0.3 0.8 150 Units V V A A
NOTE: Outputs terminated with 50 to VDD/2. See Parameter Measurement Information, "Output Load Test Circuit".
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V 5%, TA = -40C TO 85C
Symbol Parameter CLK0, CLK1 IIH Input High Current nCLK0, nCLK1 CLK0, CLK1 IIL V PP VCMR Input Low Current nCLK0, nCLK1 Peak-to-Peak Input Voltage Common Mode Input Voltage; NOTE 1, 2 VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -150 -150 0.15 1.2 0.8 1.2 VDD 150 A A A V V Test Conditions VDD = VIN = 3.465V Minimum Typical Maximum 150 Units A
NOTE 1: Common mode input voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLKx, nCLKx is VDD + 0.3V.
85401AK
www.icst.com/products/hiperclocks.html
3
REV. A FEBRUARY 22, 2005
Integrated Circuit Systems, Inc.
ICS85401
2:1 DIFFERENTIAL-TO-LVDS MULTIPLEXER
Test Conditions Minimum 200 1.05 Typical 350 1.15 Maximum 500 50 1.25 50 Units mV mV V mV
TABLE 4D. LVDS DC CHARACTERISTICS, VDD = 3.3V5%, TA = -40C TO 85C
Symbol VOD VOD VOS VOS Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change
TABLE 5. AC CHARACTERISTICS, VDD = 3.3V5%, TA = -40C TO 85C
Symbol Parameter fMAX tPD Output Frequency Propagation Delay; NOTE 1 Par t-to-Par t Skew; NOTE 2, 3 Output Rise/Fall Time Output Duty Cycle MUX Isolation 20% to 80% 125 49 -55 160 260 360 Test Conditions Minimum Typical Maximum >2.5 460 100 200 51 Units GHz ps ps ps % dB
tsk(pp)
tR / tF odc
All parameters measured at 1GHz unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
85401AK
www.icst.com/products/hiperclocks.html
4
REV. A FEBRUARY 22, 2005
Integrated Circuit Systems, Inc.
ICS85401
2:1 DIFFERENTIAL-TO-LVDS MULTIPLEXER
PARAMETER MEASUREMENT INFORMATION
3.3V 5%
VDD
SCOPE
Qx
nCLK0, nCLK1
Power Supply +
Float GND
-
LVDS
nQx
V
nCLK0, nCLK1
PP
Cross Points
V
CMR
GND
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx PART 1 Q0x nQy PART 2 Qy
nQ Q
Pulse Width t
PERIOD
tsk(pp)
odc =
t PW t PERIOD
PART-TO-PART SKEW
nCLK0, nCLK1 CLK0, CLK1 nQ Q
tPD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
80% Clock Outputs
80%
20% tR tF
20%
PROPAGATION DELAY
VDD out
OUTPUT RISE/FALL TIME
VDD

out
DC Input
LVDS
out
DC Input
LVDS
100
VOD/ VOD out
VOS/ VOS
OFFSET VOLTAGE SETUP
85401AK
DIFFERENTIAL OUTPUT VOLTAGE SETUP
www.icst.com/products/hiperclocks.html
5
REV. A FEBRUARY 22, 2005
Integrated Circuit Systems, Inc.
ICS85401
2:1 DIFFERENTIAL-TO-LVDS MULTIPLEXER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
R1 1K Single Ended Clock Input
CLKx
V_REF
nCLKx
C1 0.1u
R2 1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
3.3V LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 2. In a 100 differential transmission line environment, LVDS drivers require a matched load termination of 100 across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the un-used outputs.
3.3V
3.3V
LVDS_Driv er
+
R1 100
-
100 100 Ohm Differential Transmission Line Differiential Transmission Line
FIGURE 2. TYPICAL LVDS DRIVER TERMINATION
85401AK
www.icst.com/products/hiperclocks.html
6
REV. A FEBRUARY 22, 2005
Integrated Circuit Systems, Inc.
ICS85401
2:1 DIFFERENTIAL-TO-LVDS MULTIPLEXER
here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested
3.3V 3.3V
3.3V 1.8V
Zo = 50 Ohm
Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50
R3 50 LVPECL Zo = 50 Ohm
CLK
nCLK
HiPerClockS Input
HiPerClockS Input
R1 50
R2 50
FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER
BY
FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125
3.3V
3.3V
Zo = 50 Ohm
LVDS_Driv er
CLK
R1 100
nCLK
Receiv er
Zo = 50 Ohm
FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVDS DRIVER
BY
3.3V
3.3V
3.3V
LVPECL
Zo = 50 Ohm
C1
R3 125
R4 125
CLK
Zo = 50 Ohm
C2
nCLK
HiPerClockS Input
R5 100 - 200
R6 100 - 200
R1 84
R2 84
R5,R6 locate near the driver pin.
FIGURE 3E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER WITH AC COUPLE
85401AK
BY
www.icst.com/products/hiperclocks.html
7
REV. A FEBRUARY 22, 2005
Integrated Circuit Systems, Inc.
ICS85401
2:1 DIFFERENTIAL-TO-LVDS MULTIPLEXER
decoupling capacitor should be located as close as possible to the power pin.
APPLICATION SCHEMATIC EXAMPLE
Figure 4 shows an example of ICS85401 application schematic. This device can accept different types of input signal. In this example, the input is driven by a LVDS driver. The
3.3V
C1 0.1u
3.3V
Zo = 50
R2 100
nc GND GND VDD
16 15 14 13
Zo = 50
LVDS
1 2 3 4
nc CLK_SEL nc VDD
CLK0 nCLK0 CLK1 nCLK1
GND Q nQ GND
12 11 10 9
Zo = 50
+
R1
Zo = 50
100
-
3.3V
Zo = 50
U1 ICS85401
3.3V
R3 100
Zo = 50
LVDS
R4 1K
5 6 7 8
C2 0.1u
FIGURE 4. ICS85401 APPLICATION SCHEMATIC EXAMPLE
RELIABILITY INFORMATION
TABLE 6. JAVS. AIR FLOW TABLE
FOR
16 LEAD VFQFN
JA by Velocity (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards 51.5C/W
TRANSISTOR COUNT
The transistor count for ICS85401 is: 132
85401AK
www.icst.com/products/hiperclocks.html
8
REV. A FEBRUARY 22, 2005
Integrated Circuit Systems, Inc.
ICS85401
2:1 DIFFERENTIAL-TO-LVDS MULTIPLEXER
16 LEAD VFQFN
PACKAGE OUTLINE - K SUFFIX
FOR
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL N A A1 A3 b e ND NE D D2 E E2 L 0.25 0.30 0.25 3.0 1.25 0.50 0.18 0.50 BASIC 4 4 3.0 1.25 0.80 0 0.25 Reference 0.30 MINIMUM 16 1.0 0.05 MAXIMUM
Reference Document: JEDEC Publication 95, MO-220
85401AK
www.icst.com/products/hiperclocks.html
9
REV. A FEBRUARY 22, 2005
Integrated Circuit Systems, Inc.
ICS85401
2:1 DIFFERENTIAL-TO-LVDS MULTIPLEXER
Marking 401A 401A Package 16 Lead VFQFN 16 Lead VFQFN Shipping Packaging Tray 2500 Tape & Reel Temperature -40C to 85C -40C to 85C
TABLE 8. ORDERING INFORMATION
Part/Order Number ICS85401AK ICS85401AKT
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 85401AK
www.icst.com/products/hiperclocks.html
10
REV. A FEBRUARY 22, 2005
Integrated Circuit Systems, Inc.
ICS85401
2:1 DIFFERENTIAL-TO-LVDS MULTIPLEXER
REVISION HISTORY SHEET
Rev A A A
Table T8
Page 8 10 1 Add Schematic Layout.
Description of Change Corrected count in Ordering Information Table Pin Assignment - corrected label on pin 2.
Date 8/23/04 11/17/04 2/22/05
85401AK
www.icst.com/products/hiperclocks.html
11
REV. A FEBRUARY 22, 2005

▲Up To Search▲

Price & Availability of ICS85401

	To Download ICS85401 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .